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vitesse semiconductor corporation page 1 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 features general description the vsc8150 monitors an sonet/sdh signal in order to provide section and line data for operations, administration, maintenance, and provisioning (oam&p) at multiple sonet/sdh rates. differential pecl clock and data input receivers and a differential data output isolate the high-speed interface. low-speed ttl inputs and outputs allow the use of inexpensive programmable logic to perform oam&p functions. the vsc8150 is an ideal solution for constructing a non-intrusive sonet/sdh monitoring interface when visibil- ity of payload data is not required. functional description the vsc8150 high-speed interface receives recovered sonet/sdh data rxsin +/- and clock rxs- clkin +/- and provides a re-timed data output rxslbout +/- . internally the data is framed and sef/lof framing alarms generated. incoming b1 parity is calculated and compared with the transmitted b1 value, and detected errors are output. the 27 bytes of the ?st sts-1 transport overhead are descrambled and output for processing. vsc8150 functional block diagram ? integrated 2.488 gb/s demultiplexer ? outputs sonet/sdh transport overhead ? support for multiple sonet/sdh rates ? b1 calculation and error reporting ?lof/sef alarm generation ? serial data loopthrough output ? 100 pqfp package ? single 3.3v supply option framer b1 check 1:8 dmx descrambler control & alarm detection 311mhz internal clock source sohclk sohout[7:0] rxfpout rxfrerr rxsef rxlof b1err reset selfrdet[1:0] frdeten rxsin+/- rxsclkin+/- rxslbout+/- los overhead latch rxpclkin rxpin[7:0] ratesel[1:0] disdscrm
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 2 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 note: references (r#-#) or (o#-#) refer to the sonet requirement or option speci?ation listed in bellcore document gr-253 core issue 2. framing the frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. out-of-frame is de?ed as a state where the frame boundaries of the received sonet/sdh signal are unknown, i.e. after sys- tem reset or if for some reason the receiver loses synchronization, e.g. due to ?it slips? in-frame is de?ed as a state where the frame boundaries are known. figure 1: functional block diagram of frame acquisition circuit the receiver monitors the frame synchronization by checking for the presence of a portion of the a1/a2 framing pattern every 125us. if one or more bit errors are detected in the expected a1/a2 framing pattern rxfrerr will be asserted for 51.44ns. if framing pattern errors are detected for four consecutive frames a severely errored frame (sef) alarm will be asserted (rxsef active high) ( r5-206 ) (see figure 7and 10). the frame boundary detection/veri?ation is based on 12, 24 or 48 bits of the a1/a2 overhead (see figure 2) depending on the setting of the selfrdet input (see table 1). frame acquisition is initiated when the frdeten input is held high. this control is level sensitive and the vsc8150 will continually perform frame acquisition as long as frdeten is held high; a suggested implementation is to short frdeten logically or physically to the sef output. such an arrangement will achieve realignment within 250us or the receipt of two error free framing patterns ( r5-208 ). a frame detect based on 24 bits will result in an sef alarm at an average of no more than once every 6 min- utes assuming a ber of 10-3 ( r5-207 ). a frame detect based on 12 bits or 48 bits will result in a mean time between sef detects of 0.43 minutes and 103 minutes respectively. 1:8 dmx frame det byte align error/alarm detection frame sync. counter rxfrerr rxsef rxlof out resync frdeten seffrdet1 selfrdet0 rxsin
vitesse semiconductor corporation page 3 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 table 1: frame detection select settings figure 2: frame detection patterns loss of signal a loss of signal (los active high) input is provided to prevent noise from propagating into the overhead output logic. logic zeros will be clocked into the device when los is active high, and sef will be immediately synchronously asserted, with lof appearing 3ms afterward. if rxsclkin+/- disappears before los is asserted the part will freeze and sef/lof will never appear. loss of frame a loss of frame (lof) defect is declared (rxlof active high) when a severely errored frame (sef) condition persists for 3ms ( r6-59 ). the lof state detection is based on an integrating timer to prevent sporadic errors from not asserting lof, such as a periodic 1ms error. in the event of sporadic errors, the out of frame timer increments when rxsef = 1. it is on hold when rxsef = 0 and does not change state as long as this condition lasts for < 3 ms. the out of frame timer is reset to its initial state if the rxsef is low for > 3 ms, and an lof defect is cancelled after an in-frame condition (rxsef low) persists for a total of 3ms ( r6-61 ). multiple sonet/sdh rate functionality the vsc8150 supports three sonet/sdh rates: sts-48/stm-16, sts-12/stm-4, and sts-3/stm-1. the user is responsible for rate-provisioning the device by setting the two inputs ratesel[1:0] (see table 2). the device requires a clock rate appropriate to the selected data rate in order for internal circuitry to function correctly. lof integration timing is 3ms regardless of the rate selected. function selfrdet1 selfrdet0 24 bits 1 0 48 bits 0 1 12 bits 0 0 frame detection disabled 1 1 a1 (0xf6) a1 (0xf6) a1 (0xf6) a2 (0x28) a2 (0x28) a2 (0x28) 48 bits 24 bits 12 bits
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 4 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 table 2: sonet/sdh rate select settings descrambler framed sonet/sdh bytes are descrambled using a frame synchronous descrambler with generating poly- nomial 1 + x6 + x7 and a sequence length of 127. the scrambling algorithm is reset to an all 1's state immedi- ately following the z0 byte ((sonet 192 x 3) | (sdh 64x9) = 577th received byte in frame). all a1, a2, and j0/z0 bytes are not descrambled ( r5-6 ). b1 error monitoring the section bit-interleaved parity (bip-8) error detection code b1 will be calculated for every frame before de-scrambling and compared to its extracted value after de-scrambling the b1 value in the following frame (r3- 16). if b1 errors were detected in the previous frame a series of pulses will appear on the b1err output, begin- ning approximately 60ns after the b1 byte is received. the number of pulses indicates the quantity of errored bit positions detected; the absence of pulses indicates no received b1 errors, and eight pulses would indicate the maximum number of received b1 errors. the pulses are eight parallel clocks wide (25.7ns at 2.488ghz rxs- clkin), and spaced apart by the same amount (see ?ure 10). overhead byte read out overhead bytes are descrambled (with the exception of a1, a2, and j0) and output from sohout[7:0] in the order of their appearance in the frame. only the bytes from the ?st sts-1 frame or the ?st, fourth, and seventh columns of the ?st stm-1 frame are presented (see figure 6). accompanying the data from the sohout[7:0] output are the output clock sohclk and frame pulse rxfpout (see figures 8 and 9). the sohout output is undened when sef is high. the user should be aware that overhead data from one frame prior to the rxfrerr pulse could be corrupted and should not be used for oam&p functions. fpga interface rxfpout is used to provide a reference point to the 27 byte sequence of overhead bytes and clocks. it is suggested that the sohclk be used to clock an external counter with rxfpout used as the counter reset. the count value can be used as the overhead byte address, and rxpout will reset the counter when it reaches a logical value of 27. the high order bit of this counter is useful for indicating when the b1 pulse train results can be read. a block diagram illustrates this arrangement more clearly. (see figure 3). function ratesel1 ratesel0 sts-3/stm-1 0 1 sts-12/stm-4 1 0 sts-48/stm-16 0 0 invalid 1 1
vitesse semiconductor corporation page 5 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 figure 3: suggested vsc8150 system implementation high speed interface serial data received on the rxsin+/- inputs is retimed on the falling edge of rxsclkin+/- clock and appears on the serial loopback output rxslbout+/- (see figure 11). this interface will pass data at all fre- quencies from dc to 2.5ghz, and does not necessarily have to retime sonet/sdh data. inputs rxsin+/- and rxsclkin+/- do not have internal termination resistors, but internal biasing resis- tors provide a bias voltage suitable for ac coupling (see figure 4). in most situations these inputs will have high transition density and little dc offset. however, in cases where this does not hold, direct dc connection is possible. all serial data and clock inputs have the same cir- cuit topology, as shown in ?ure 4. the reference voltage is created by a resistor divider as shown. if the input signal is driven differentially and dc-coupled to the part, the mid-point of the input signal swing should be cen- tered about this reference voltage and not exceed the maximum allowable amplitude. for single-ended, dc- coupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. the external reference should have a nominal value equivalent to the common mode switch point of the dc coupled signal, and can be con- nected to either side of the differential gate. b1err sohout[7:0] sohclk rxfpout vsc8150 fpga 27x8 register file d[7:0] q[7:0] ra[4:0] wa[4:0] 5 bit counter 4 bit counter reset reset q[2:0] q4 oam&p b1 count b1 valid frame count oh data rxsef rxlof rxfrerr system clock los
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 6 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 figure 4: high speed serial clock and data inputs figure 5: high speed output termination v te r m v cc = 3.3v v ee = 0v 1.65v 1.65v r | | = 1.5k w c in c se v ee chip boundary c in typ = 100 pf c se typ = 100 pf for single ended applications. (capacitor values z o r t = z o are selected for di = 2.5gb/s.) v cc v ee z 0 = 50 50 100 50 pre-driver
vitesse semiconductor corporation page 7 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 the high speed data and clock output drivers consist of a differential pair designed to drive a 50 w transmis- sion line. the transmission line should be terminated with a 100 w resistor at the load between true and comple- ment outputs (see figure 5). no connection to a termination voltage is required. the output driver is back terminated to 50 w on-chip, providing a snubbing of any re?ctions. if used single-ended, the high speed output driver must still be terminated differentially at the load with a 100 w resistor between true and complement out- puts. figure 6: transport overhead note: only bytes from the ?st sts-1 of the sonet signal are output from the sohout[7:0] port. sts-48(2) sts-48(1) stm-1(1) framing a1 framing a2 sts-48 j0 bip-8 sts-48 b1 orderwire e1 user f1 datacom d1 pointer h1 pointer action h3 bip-8 sts-48(1) b2 aps k1 aps k2 sync s1 rei-l m0 orderwire e2 datacom d2 datacom d3 pointer h2 datacom d4 datacom d5 datacom d6 datacom d7 datacom d8 datacom d9 datacom d10 datacom d11 datacom d12 sts-48(3) sts-48(48)
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 8 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 figure 7: functional framing timing diagram (sts-48/stm-16 mode) figure 8: functional overhead readout timing j0 j0 j0 j0 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af rxpclkin rxpin[7:0] rxfpout rxfrerr b7 b6 b5 b4 b3 b2 b1 b0 rxsclkin rxsin b0 rxsef z2 e2 a1 a2 j0 b1 e1 f1 sohout[7:0] sohclk rxfpout
vitesse semiconductor corporation page 9 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 ac timing characteristics figure 9: overhead output timing diagram table 3: overhead output timing (sts-48/stm-16 mode) note: generated waveforms are synchronous and assume a 2.488ghz rxsclkin signal. table 4: overhead output timing (sts-12/stm-4 mode) note: generated waveforms are synchronous and assume a 622mhz rxsclkin signal. table 5: overhead output timing (sts-3/stm-1 mode) note: generated waveforms are synchronous and assume a 155mhz rxsclkin signal. parameter description min typ max units t ohsu overhead output setup time with respect sohclk 75 ns t ohh overhead output hold time with respect sohclk 75 ns t ohclkw overhead output clock period 154 ns t fpsu frame pulse setup time with respect to sohclk 90 ns t fpw frame pulse width 50 ns parameter description min typ max units t ohsu overhead output setup time with respect sohclk 75 ns t ohh overhead output hold time with respect sohclk 75 ns t ohclkw overhead output clock period 154 ns t fpsu frame pulse setup time with respect to sohclk 116 ns t fpw frame pulse width 50 ns parameter description min typ max units t ohsu overhead output setup time with respect sohclk 100 ns t ohh overhead output hold time with respect sohclk 50 ns t ohclkw overhead output clock period 154 ns t fpsu frame pulse setup time with respect to sohclk 150 ns t fpw frame pulse width 50 ns t ohsu t ohh t ohclkw sohout[7:0] e2 a1 a2 c1/j0 sohclk t fpsu t fpw rxfpout
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 10 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 figure 10: framing and b1 error output timing table 6: framing and b1 error output timing (sts-48/stm-16 mode) note: generated waveforms are synchronous and assume a 2.488ghz rxsclkin signal. table 7: framing and b1 error output timing (sts-12/stm-4 mode) note: generated waveforms are synchronous and assume a 622mhz rxsclkin signal. parameter description min typ max units t fpw frame pulse width 51.4 ns t ferrsu frame boundary error delay with respect to rxfpout 61.2 ns t ferrpw frame boundary error pulse width high 25.7 ns t sefsu sef transition delay time with respect to rxfpout 48.3 ns t b1su b1 pulse train delay with respect to rxfpout 14 m s t b1pwh b1 error pulse width high 25.7 ns t b1pwl b1 error pulse width low 25.7 ns parameter description min typ max units t fpw frame pulse width 51.4 ns t ferrsu frame boundary error delay with respect to rxfpout 64.4 ns t ferrpw frame boundary error pulse width high 51.4 ns t sefsu sef transition delay time with respect to rxfpout 51.4 ns t b1su b1 pulse train delay with respect to rxfpout 14 m s t b1pwh b1 error pulse width high 103 ns t b1pwl b1 error pulse width low 103 ns b1err rxsef rxfpout rxfrerr note: waveforms not to scale t b1su t b1pwl t b1pwh t ferrsu t sefsu t ferrpw t fpw
vitesse semiconductor corporation page 11 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 table 8: framing and b1 error output timing (sts-3/stm-1 mode) note: generated waveforms are synchronous and assume a 155mhz rxsclkin signal. figure 11: serial data input timing diagram table 9: serial data input timing parameter description min typ max units t fpw frame pulse width 51.4 ns t ferrsu frame boundary error delay with respect to rxfpout 0 ns t ferrpw frame boundary error pulse width high 51.4 ns t sefsu sef transition delay time with respect to rxfpout 103 ns t b1su b1 pulse train delay with respect to rxfpout 13.96 m s t b1pwh b1 error pulse width high 409 ns t b1pwl b1 error pulse width low 409 ns parameter description min typ max units t rxsclkin serial receive clock period 401.9 - - ps t rxssu serial receive input data rxsin setup time with respect to falling edge of rxsclkin+ 100 - - ps t rxsh serial receive input data rxsin hold time with respect to falling edge of rxsclkin+ 75 - - ps t rxslbout propagation delay from falling edge of rxsclkin+ 430 - 820 ps t rxssu t rxsh t rxsclkin rxsclkin- rxsclkin+ rxsin+ rxsin- t rxslbout rxslbout+ rxslbout-
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 12 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 dc characteristics table 10: high-speed differential ecl inputs and outputs (hsecl) note: hsecl inputs are not terminated on chip (high impedance inputs). table 11: ttl inputs and outputs table 12: power supply currents (v mm = v cc = +3.3v, outputs open) table 13: power supply currents (v mm = +2.0v, v cc = +3.3v, outputs open) parameter description min typ max units conditions v od output differential voltage (peak to peak, single-ended) 550 - 1200 mv load = 100 ohms across rxslbout+/? at receiver v ocm output common-mode voltage 2100 - 3000 mv load = 100 ohms across rxslbout+/? at receiver t rf output rise / fall - 100 - ps r o output impedance 40 - 60 ohms v id input differential voltage 200 - mv ac coupled, internally biased to vcc/2 parameter description min typ max units conditions v oh output high voltage 2.4 - - v i oh = -8ma v ol output low voltage 0 - 0.4 v i ol = 8ma v ih input high voltage 2.0 - vcc + 1.0v v v il input low voltage 0 - 0.8 v i ih input high current - - 500 ua v in = 2.4v i il input low current -50 - - ua v in = 0.4v parameter description (max) units i ttl power supply current from v cc 850 ma p d power dissipation 2.95 w parameter description (max) units i ttl power supply current from v cc 420 ma i mm power supply current from v mm 430 ma p d power dissipation 2.35 w
vitesse semiconductor corporation page 13 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 absolute maximum ratings power supply voltage ( v cc ) potential to gnd ............................................................................ -0.5 v to +4.3 v ttl input voltage applied ..................................................................................................... ......-0.5 v to + 5.5v ecl input voltage applied ................................................................................................... +0 .5 v to v tt -0.5 v output current ( i out ) .............................................................................................................................. ..... 50 ma case temperature under bias ( t c ) ................................................................................................-55 o to + 125 o c storage temperature ( t stg )............................................................................................................-65 o to + 150 o c note: caution: stresses listed under ?bsolute maximum ratings?may be applied to devices one at a time without causing per- manent damage. functionality at or exceeding the values listed is not implied. exposure to these values for extended peri- ods may affect device reliability. recommended operating conditions power supply voltages ( v cc )...............................................................................................................+3.3v % power supply voltages ( v mm ) ..............................................................................................................+2.0v % commercial operating temperature range ( t ) .................................................................................... 0 o to 85 o c notes: (1) lower limit of speci?ation is ambient temperature and upper limit is case temperature. (2) customer may require cooled/heatsink environment to meet thermal requirements of 100pqfp. (3) contact factory for package thermal performance information. esd ratings proper esd procedures should be used when handling this product. the vsc8150 is rated to the following esd voltages based on the human body model: 1. all pins are rated at or above 1500v. 5 5
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 14 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 vsc8150 package pin diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vcc vee vmm vcc vcc nc nc vcc rxsclkin+ rxsclkin vee rxsin+ rxsin vee rxslbout+ rxslbout vcc nc nc vcc vcc vmm vee vcc nc vcc vmm vcc vee sohout6 sohout5 vee sohout4 sohout3 vcc vee sohclk sohout2 vcc vee sohout1 sohout0 vee nc nc vcc vcc vmm vcc test test test vcc vcc test test vee test test vmm test test vcc vcc test test vmm reset disdscrm vee test test vcc vcc nc test ratesel0 vcc vcc selfrdet0 selfrdet1 vee frdeten ratesel1 vmm rxfpout rxfrerr vcc vee b1err nc vmm rxsef rxlof vee nc sohout7 vee vcc los
vitesse semiconductor corporation page 15 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 package pin description table 14: pin de?itions signal pin i/o level pin description vcc 1 pwr +3.3v vee 2 pwr gnd vmm 3 pwr +2.0v vcc 4 pwr +3.3v vcc 5 pwr +3.3v nc 6 -- leave unconnected nc 7 -- leave unconnected vcc 8 pwr +3.3v rxsclkin+ 9 i pecl demux clk input rxsclkin- 10 i pecl demux clk input vee 11 pwr gnd rxsin+ 12 i pecl demux data input rxsin- 13 i pecl demux data input vee 14 pwr gnd rxslbout+ 15 o pecl demux data output rxslbout- 16 o pecl demux data output vcc 17 pwr +3.3v nc 18 -- leave unconnected nc 19 -- leave unconnected vcc 20 pwr +3.3v vcc 21 pwr +3.3v vmm 22 pwr +2.0v vee 23 pwr gnd vcc 24 pwr +3.3v test 26 i gnd test input test 27 i gnd test input vcc 28 pwr +3.3v vcc 29 pwr +3.3v test 30 i gnd test input test 31 i gnd test input vee 32 pwr gnd test 33 i gnd test input test 34 i gnd test input vmm 35 pwr +2.0v test 36 i gnd test input test 37 i gnd test input
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 16 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 vcc 38 pwr +3.3v vcc 39 pwr +3.3v test 40 i gnd test input test 41 i gnd test input vmm 42 pwr +2.0v reset 43 i ttl active high (tie to gnd) disdscrm 44 i ttl descrambler disable vee 45 pwr gnd test 46 i gnd test input test 47 i gnd test input vcc 48 pwr +3.3v vcc 49 pwr +3.3v nc 50 -- leave unconnected test 51 i gnd test input vcc 52 pwr +3.3v vmm 53 pwr +2.0v vcc 54 pwr +3.3v vcc 55 pwr +3.3v nc 56 nc test output nc 57 nc test output vee 58 pwr gnd sohout0 59 o ttl overhead output bus sohout1 60 o ttl overhead output bus vee 61 pwr gnd vcc 62 pwr +3.3v sohout2 63 o ttl overhead output bus sohclk 64 o ttl overhead output clock vee 65 pwr gnd vcc 66 pwr +3.3v sohout3 67 o ttl overhead output bus sohout4 68 o ttl overhead output bus vee 69 pwr gnd sohout5 70 o ttl overhead output bus sohout6 71 o ttl overhead output bus vee 72 pwr gnd vcc 73 pwr +3.3v vmm 74 pwr +2.0v vcc 75 pwr +3.3v table 14: pin de?itions signal pin i/o level pin description
vitesse semiconductor corporation page 17 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 table 15: power supply summary los 76 i ttl loss of signal vcc 77 pwr +3.3v vee 78 pwr gnd sohout7 79 o ttl overhead output bus nc 80 -- leave unconnected vee 81 pwr gnd rxlof 82 o ttl loss of frame rxsef 83 o ttl severely errored frame vmm 84 pwr +2.0v nc 85 -- leave unconnected b1err 86 o ttl b1 error pulse output vee 87 pwr gnd vcc 88 pwr +3.3v rxfrerr 89 o ttl frame error detect rxfpout 90 o ttl frame pointer output vmm 91 pwr +2.0v ratesel1 92 i ttl sts-12/stm-4 select frdeten 93 i ttl frame detect enable vee 94 pwr gnd selfrdet1 95 i ttl frame mode select selfrdet0 96 i ttl frame mode select vcc 97 pwr +3.3v vcc 98 pwr +3.3v ratesel0 99 i ttl sts-3/stm-1 select test 100 i gnd test input signal pin i/o level pin description vcc 1,4,5,8,17,20,21, 24,28,29,38,39,48, 49,52,54,55,62,66, 73,75,77,88,97,98 pwr +3.3v vmm 3,22,35,42,53,74, 84,91 pwr +2.0v connect to +3.3v for single supply con?uration vee 2,11,14,23,32,45, 58,61,65,69,72,78, 81,87,94 pwr gnd table 14: pin de?itions signal pin i/o level pin description
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 18 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0 package information notes: (1) drawings not to scale. (2) all units in millimeters unless otherwise noted 100 pqfp package drawings package #: 101-318-3 issue #: 1 r r 1 a a 1 b l 0.25 0.17 max q 6 4 10 o typ 10 o typ a 2 e a e e 1 d d 1 heatsink intrusion .0127 max exposed heatsink 6.86 .50 dia. key mm tolerance a 2.35 max a1 0.25 max a2 2.00 +.10/-.05 d 17.20 .25 d1 14.00 .10 e 17.20 .25 e1 14.00 .10 l .88 +.15/-.10 e .50 basic b .22 .05 q 0 -7 r .30 typ r1 .20 typ
vitesse semiconductor corporation page 19 10/12/98 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 vitesse semiconductor corporation preliminary data sheet v sc8150 2.488gb/s sonet/sdh overhead monitor g52186-0, rev. 3.0 ordering information the order number for this product is formed by a combination of the device number, and package type. notice this document contains preliminary information about a new product in the preproduction phase of devel- opment. the information in this document is based on initial product characterization. vitesse reserves the right to alter speci?ations, features, capabilities, functions, manufacturing release dates, and even general availabil- ity of the product at any time. the reader is cautioned to con?m this datasheet is current prior to using it for design. warning vitesse semiconductor corporations product are not intended for use in life support appliances, devices or systems. use of a vitesse product in such applications without the written consent is prohibited. vsc8150 qq device type vsc8150: package 2.488gb/s overhead monitor qq: 100 pqfp, 14x14mm body
vitesse semiconductor corporation preliminary data sheet vsc8150 2.488gb/s sonet/sdh overhead monitor page 20 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ?805/388-3700 ?fax: 805/987-5896 10/12/98 g52186-0, rev. 3.0

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